The present invention relates to overcoming the problem of latch-up in CMOS circuitry.
This problem can be understood most easily with reference to FIG. 1 which is a representative cross-sectional view of a portion of a standard N-well CMOS transistor arrangement. As illustrated, FIG. 1 includes a P-type substrate 10 having an N-well 12. Within the N-well 12 are a P+ moat 14, a gate 16, and another P+ moat 18. Elements 14, 16 and 18 form an MOS device. Moat 14 is connected to a voltage source Vcc. Also within well 12 is an N+ moat 20 connected also to Vcc.
Outside of moat 12, there is an N+ moat 22, a gate 24 and another N+ moat 26. Elements 22, 24 and 26 form another MOS transistor. A P+ moat 28 is also included, and moats 26 and 28 are grounded by connection to Vss.
Certain parasitic structures are illustrated in FIG. 1. An NPN transistor 30 is shown at the left side in the P substrate, and a PNP transistor 32 is shown at the right in the N-well. The collector of transistor 30 is the N-well 12, its base is the P substrate and its emitter is N+ moat 26. With regard to transistor 32, the collector is the P type substrate 10, the base is the N-well 12, and the emitter is the P+ type moat 14.
There are resistances between the bases of transistors 30 and 32 between the substrate or well contacts. With respect to transistor 30, a substrate resistance 34 exists between the base of transistor 30 and moat 28. A node 36 is located at the base of transistor 30. With respect to transistor 32, a resistance 38 exists between the base and the N+ moat 20. A node 40 is located schematically between resistance 38 and the base of transistor 32. It will be seen that mode 36 is connected electrically to the base of transistor 30 and to the collector of transistor 32. Similarly node 40 is connected electrically to the base of transistor 32 and to the collector of transistor 30.
The problem of latch-up can now be illustrated. If transistor 32 is turned on, a current passes through node 36, causing the voltage at node 36 to rise. This turns on transistor 30. This in turn causes a current at node 40, which pulls down node 40 in voltage. This turns on transistor 32 even harder. This causes the current to increase, causing the voltage at node 36 to rise even more. This in turn causes transistor 30 to turn on even harder, which has the effect of increasing the current through node 40. It will be seen that this is an ever increasing routine. This circumstance can be triggered by a base current in either transistor 30 or transistor 32. It can be induced by a wide variety of things, including rapid changes in a power supply voltage, light, radiation, input and output over voltage, and on-chip capacitive disturbances. When this occurs, it is referred to by the art as "latch-up."
It is therefore the principal object of the present invention to devise a method and apparatus which overcomes the problem of latch-up in CMOS circuits.